fn4640 rev 5.00 page 1 of 9 november 18, 2004 fn4640 rev 5.00 november 18, 2004 hip1011b pci hot plug controller datasheet the hip1011b, the third product in the hip1011 family, is an electronic circuit breaker that monitors, reports and protects circuits from excessive load currents. as a pin-for-pin drop-in alternative offering similar functionality to the widely used hip1011, the hip1011b is co mpatible with compactpci peripheral boards and pci hot plug systems where voltage ?health? monitoring and reporting are centralized by the system controller ic. the hip1011b does not monitor nor respond to under voltage condit ions thus making control of a wide range of voltages possible. the hip1011b creates a small and simple yet complete power control solution to control the four independent supplies (+5v, +3.3v, +12v, and -12v) found in pci and compactpci systems. for the +12v and -12v supplies, overcurrent protection is provi ded internally with integrated current sensing fet switches. for the +5v and +3.3v supplies, overcurrent protecti on is provided by sensing the voltage across the external current-sense resistors. the pwron input controls the state of both internal and external switches. during an overcurrent condition on any output, all mosfets are latched-off and a low (0v) is asserted on the fltn output. the fltn latch is cleared when the pwron input is toggled low again. during initial power-up of the main v cc supply (+12v), the pwron input is inhibited from turning on the switches, and the latch is held in the reset state until the v cc input is greater than 10v. user programmability of the ov ercurrent threshold, response time and turn-on slew rate is provided. a resistor connected to the ocset pin programs the overcurrent thresholds. a capacitor may be added to the fltn pin to adjust the fault reporting and power-supply latch-off response times after an over-current event. capacitors connected to the gate pins determine the turn-on rate. features ? allows for system centralized voltage monitoring ? adjustable delay to fault notification and latch-off ? controls four supplies: +5v, +3.3v, +12v, and -12v ? internal mosfet switches for +12v and -12v outputs ? ? p interface for on/off control and fault reporting ? adjustable overcurrent protection for all supplies ? provides overcurrent fault isolation ? adjustable turn-on slew rate ? minimum parts count solution ? no charge pump ? pb-free available (rohs compliant) applications ? pci hot plug ? compactpc i pinout hip1011b (soic) top view ordering information part number temp. range ( o c) package pkg. dwg. # hip1011bcb 0 to 70 16 ld soic m16.15 hip1011bcb-t 0 to 70 tape and reel HIP1011BCBZA (see note) 0 to 70 16 ld soic (pb-free) m16.15 HIP1011BCBZA-t (see note) 0 to 70 tape and reel (pb-free) note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible wit h both snpb and pb-free soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temperatures that mee t or exceed the pb-free requirements of ipc/jedec j std-020c. 9 10 11 12 13 14 16 15 8 7 6 5 4 3 2 1 m12vin fltn 3v5vg v cc 12vin 3visen ocset 3vs m12vo 12vg gnd 12vo m12vg 5visen 5vs pwron no t r e c o m m e n d e d f o r n e w d e s i g n s no r e co m m e n de d r e p l a ce m e nt c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - int e r s i l o r w w w . i n t e r s i l . c o m /t s c
hip1011b fn4640 rev 5.00 page 2 of 9 november 18, 2004 typical application simplified schematic 12v, m12vin fltn 3v5vg v cc 12v in 3visen 3vs ocset m12vo 12vg gnd 12vo 5visen 5vs pwron m12vg hip1011b 3.3v, 12v input 5v, -12v, 5v input -12v input power control input 0.033 ? f 0.033 ? f 6.04k ? fault output (active low) (optional) 5m ? , 1% 0.033 ? f note: all capacitors are ? 10%. 1% 3.3v input 5m ? , 1% 7.6a out 0.5a out 0.1a out 5a out huf761315k8 fltn 5vs 3v5vg 5visen 3vs ocset 3visen 12vin 12vg 12vo m12vin m12vg m12vo pwron gnd 12vin power-on reset v cc v cc v cc 100 ? a 0.3 ? 0.7 ? fault latch v ocset 5v zener reference v cc 5v ref v ocset /17 v ocset /0.8 v cc set (low = fault) reset v cc low = fault low when v cc < 10v high = switches on high = fault + - comp - + comp - + v ocset /13.3 + - comp - + + - v cc v cc v ocset /3.3 comp - + + - v cc
hip1011b fn4640 rev 5.00 page 3 of 9 november 18, 2004 pin descriptions pin designator function description 1 m12vin -12v input -12v supply input. also provid es power to the -12v overcurrent circuitry. 2 fltn fault output 5v cmos fault output; low = fault. a capacitor may be placed from this pin to ground to provide delay time to fault notifi cation and power supply latch-off. 3 3v5vg 3.3v/5v gate output drive the gates of the 3.3v and 5v mosfets. connect a capacitor to ground to set the start- up ramp. during turn on, this capacitor is charged with a 25 ? a current source. 4v cc 12v v cc input connect to unswitched 12v supply. 512v in 12v input switched 12v supply input. 6 3visen 3.3v current sense connect to the load side of the current sense resistor in series wi th source of external 3.3v mosfet. this pin tied to gnd wh en fet switch outputs disabled. 7 3vs 3.3v source connect to source of 3.3v mosfet . this connection along with pin 6 (3visen) senses the voltage drop across the sense resistor. 8 ocset overcurrent set connect a resistor from this pin to ground to set the overcurrent trip point of all four switches. all four over current trips can be programmed by c hanging the value of this resistor. the default (6.04k ?? 1%) is compatible with the maximum a llowable currents as outlined in the pci specification. 9 pwron power on control controls all four switches. high to turn switches on, low to turn them off. 10 5vs 5v source connect to source of 5v mosfet switch . this connection along with pin 11 (5visen) senses the voltage drop across the sense resistor. 11 5visen 5v current sense connect to the load side of the current sense resistor in series with source of external 5v mosfet. this pin tied to gnd when fet switch outputs disabled. 12 12vo switched 12v output switched 12v output. this pin tied to gnd when fet switch outputs disabled. 13 gnd ground connect to common of power supplies. 14 12vg gate of internal pmos connect a capacitor between 12vg and 12vo to set the start up ramp for the +12v supply. this capacitor is charged with a 25 ? a current source during start-up. 15 m12vg gate of internal nmos connect a capacitor between m12vg and m12vo to set the start-up ramp for the m12v supply. this capacitor is charged with 25 ? a during start-up. 16 m12vo switched -12v output switched 12v output. this pin tied to gnd when fet switch outputs disabled.
hip1011b fn4640 rev 5.00 page 4 of 9 november 18, 2004 absolute maximum ratings thermal information v cc , 12vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0v 12vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v12v in + 0.5v 12vo, 12vg, 3v5vg . . . . . . . . . . . . . . . . . . . . -0.5v to v cc + 0.5v m12vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15.0v to + 0.5v m12vo, m12vg. . . . . . . . . . . . . . . . . . . . . v m12vin -0.5v to + 0.5v 3visen, 5visen . . . . . . . . . . . -0.5v to the lesser of v cc or + 7.0v voltage, any other pin . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 7.0v 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8a esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kev (hbm) operating conditions vcc supply voltage range. . . . . . . . . . . . . . . . . +10.8v to +13.2v 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.5a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +0.1a temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ? ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . 125 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) die characteristics number of transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ? ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board in free air. see tech b rief tb379 for details. 2. all voltages are relative to gnd, unless otherwise specified. electrical specifications nominal 5v and 3.3v input supply voltages, v cc = 12vin = 12v, m12vin = -12v, t a = t j = 0 to 70 o c, unless otherwise specified parameter symbol test conditions min typ max units 5v/3.3v supply control 5v overcurrent threshold i oc5v see figure 1, typical application - 8 - a 5v overcurrent threshold voltage v oc5v_1 v ocset = 0.6v 30 36 42 mv 5v overcurrent threshold voltage v oc5v_2 v ocset = 1.2v 66 72 79 mv 5v turn-on time (pwron high to 5vout = 4.75v) t on5v c 3v5vg = 0.022 ? f, c 5vout = 2000 ? f, r l = 1 ? -6.5- ms 5vs input bias current ib 5vs pwron = high -40 -26 -20 ? a 5visen input bias current ib 5visen pwron = high -160 -140 -110 ? a 3v overcurrent threshold i oc3v see figure 1, typical application 10 a 3v overcurrent threshold voltage v oc3v_1 v ocset = 0.6v 42 49 56 mv 3v overcurrent threshold voltage v oc3v_2 v ocset = 1.2v 88 95 102 mv 3v turn-on time (pwron high to 3vout = 3.00v) t on3v c 3v5vg = 0.022 ? f, c 3vout = 2000 ? f, r l = 0.43 ? -6.5- ms 3vs input bias current ib 3vs pwron = high -40 -26 -20 ? a 3visen input bias current ib 3visen pwron = high -160 -140 -110 ? a 3v5vg v out high v out_hi_35vg 3v5vg iout = 5 ?? 11 11.7 - v gate output charge current ic 3v5vg pwron = high, v 3v5vg = 2v 22.5 25.0 27.5 ? a gate turn-on time (pwron high to 3v5vg = 11v) t on3v5v c 3v5vg = 0.1 ? f - 280 500 ? s gate turn-off time t off3v5v c 3v5vg = 0.1 ? f, 3v5vg from 9.5v to 1v - 13 17 ? s gate turn-off time c 3v5vg = 0.022 ? f, 3v5vg falling 90% to 10% - 2 - ? s
hip1011b fn4640 rev 5.00 page 5 of 9 november 18, 2004 +12v supply control on resistance of internal pmos r ds(on)12 pwron = high, i d = 0.5a, t a = t j = 25 o c 0.18 0.3 0.35 ? overcurrent threshold i oc12v_1 v ocset = 0.6v 0.6 0.75 0.9 a overcurrent threshold i oc12v_2 v ocset = 1.2v 1.25 1.50 1.8 a gate charge current ic 12vg pwron = high, v 12vg = 3v 22.5 25 28.5 ? a turn-on time (pwron high to 12vg = 1v) t on12v c 12vg = 0.022 ? f-1620ms turn-off time t off12v c 12vg = 0.1 ? f, 12vg - 9 12 ? s turn-off time c 12vg = 0.022 ? f, 12vg rising 10% - 90% - 3 - ? s -12v supply control on resistance of internal nmos r ds(on)m12 pwron = high, i d = 0.1a, t a = t j = 25 o c 0.5 0.7 0.9 ? overcurrent threshold i oc12v_1 v ocset = 0.6v 0.15 0.18 0.25 a overcurrent threshold i oc12v_2 v ocset = 1.2v 0.30 0.37 0.50 a gate output charge current ic m12vg pwron = high, v 3vg = -4v 22.5 25 28.5 ? a turn-on time (pwron high to m12vg = -1v) t onm12v c m12vg = 0.022 ? f - 160 300 ? s turn-on time (pwron high to m12vo = -10.8v) t onm12v c m12vg = 0.022 ? f, c m12vo = 50 ? f, r l = 120 ? -16-ms turn-off time t offm12v c m12vg = 0.1 ? f, m12vg - 18 23 ? s turn-off time c m12vg = 0.022 ? f, m12vg falling 90% to 10% - 3 - ? s m12vin input bias current ib m12vin pwron = high - 2 2.6 ma control i/o pins supply current i vcc 455.8ma ocset current i ocset 95 100 105 ? a overcurrent fault response time t oc - 500 960 ns pwron threshold voltage v thpwron 0.8 1.6 2.1 v fltn output low voltage v fltn,ol i fltn = 2ma - 0.6 0.9 v fltn output high voltage v fltn,oh i fltn = 0 to -4ma 3.9 4.3 4.9 v fltn output latch threshold v fltn,th 1.45 1.8 2.25 v 12v power on reset threshold v por,th v cc voltage falling 8.7 9.4 9.9 v electrical specifications nominal 5v and 3.3v input supply voltages, v cc = 12vin = 12v, m12vin = -12v, t a = t j = 0 to 70 o c, unless otherwise specified (continued) parameter symbol test conditions min typ max units
hip1011b fn4640 rev 5.00 page 6 of 9 november 18, 2004 adjusting the fault reporting and power supply latch-off delay times figure 5 illustrates the relationship between the fltn signal and the gate drive outputs. duration a , indicates the time between fltn starting to transition from high to low, (indicating a fault has occurred) and the start of the gate drive outputs latching off. the latch-off is initiated by the falling fltn signal reaching the output latch threshold voltage, vfltn, th. for additional details and wave forms see hip1011a data sheet fn4631. table 1 illustrates the effect of the fltn capacit or on the response times. typical performance curves figure 1. r on vs temperature figure 2. oc vth vs temperature (vr ocset = 1.21v) figure 3. ocset current vs temperature figure 4. v cc power on reset vth vs temperature 340 320 300 280 260 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 1000 900 800 700 600 pmos r on + 12 (m ? ) nmos r on -12 (m ? ) temperature ( o c) pmos +12 r on nmos -12 r on 105 95 85 75 65 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 oc vth (mv) temperature ( o c) 5v ocvth 3v ocvth 102 101 100 99 98 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 i ocset ( ? a) temperature ( o c) 9.5 9.4 9.3 9.2 9.1 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 v por vth (v) temperature ( o c) table 1. response time table 0.001 ? f0.1 ? f10 ? f 3v5vg response a 0.85 ? s37 ? s3.8ms figure 5. timing diagram 3v5vg fltn a t1 t2 v fltn,th
hip1011b fn4640 rev 5.00 page 7 of 9 november 18, 2004 applications implementing the hip1011b in the compactpci hot swap application this application offers to the compactpci peripheral board designer programmable over current (oc) protection, programmable delays to latch off, and soft start ramp turn on for all four supplies with simu ltaneous latch off upon oc fault detection. figure 6 illustrates the hip 1011eval2 evaluation board for compactpci hot swap implementation. the shaded components are the external components necessary to accomplish both controlled power up and turn-on. for minimum pcb area single gate logic can be used. insertion sequence because of the staggered pin lengths in the compactpci connector, as the board is inserted into the slot, the ground bus plane is connected first via the longest pins referencing the hip1011b by way of the pwron, ocset and gnd pins through r4 and r3. additionally the three-state driver, u1 address line is referenced through r6. subsequently the medium length pins engage to connect the +3.3v, +5v, +12v, -12v lines to the inputs, activating the hip1011b, and the 2 logic devices, u1 and u2. at this time the hip1011b is in control holding off all the mosfet switches, as pwron is being held low. with the logic devices powered the inverter u2 input is pulled high putting a low on the three-state driver u1 input which is passed through to the pwron pin. upon complete insertion the shortest length pin, ?board present? which is tied to ground on the backplane finally contacts the inverter input. the inverter output pulls high turning on the hip1011b through u1 thus, the board is fully powered on only upon complete insertion. fault reset if an overcurrent condition is detected on the board by the hip1011b the fltn signal transitions low, once the v fltn,th is reached all the swit ches are simultaneously switched off protecting the system, the board and its components. the system controller is notified of the fault occurrence by the fltn signal. reset of the faulted card is accomplished by a positive pulse on the three-state oe input. the pulse puts u1 output into a high z state allowing r4 to pull the hip1011b pwron pin low, resetting the hip1011b. the hip1011b switches turn back on when u1 oe input returns to a low state resulting in pwron going high. the reset pulse can be generated by either the system restart/reset to the master board or from the master system board to any of the peripheral boards in the system. q1, q2 c2 q3, q4 r3 c3 c4 c1 m12vin fltn 3v5vg v cc 12vin 3visen 3vs ocset m12vo 12vg gnd 12vo 5visen 5vs pwron m12vg hip1011 12v input 5v input -12v input r1 3.3v input r2 fltn 3.3vout 5vout -12v out +12vout pulse high to reset fault oe board present pin on backplane r4 r6 u1 u2 r5 figure 6. hip1011b compactpci application circuit notes: 3. each test point (tp) on hip1011eval2 refers to device pin number. 4. signal_gnd, shield_gnd and shortpin_gnd can be jumpered together for ease of evaluation. 5. hip1011b devices can be placed into hip1011eval2 board for eval uation or contact intersil for a hip1011b equipped evaluation board.
hip1011b fn4640 rev 5.00 page 8 of 9 november 18, 2004 hip1011 split load application all of the members of the hip1011 family, including the hip1011b, can be used in an application where two electrically isolated loads are to be powered from a common bus. this may occur in a system that has a power management feature controlled by a system controller ic invoking a sleep or standby state. thus one load can be shut down while maintaining power to a second isolated circuit. the circuit shown in figure 7 shows the external fets, and sense resistor configuration for the 3.3v and/or 5v load that has such a requirement. the hi p1011 is represented by pin names in rectangles. q1 and q2 are the n-channel fets for each load on this rail, these are sized appropriately for each load. r1 and r2 are needed to pull down the supply slot pins or load when slot power is disabled as the load discharge fets (q3) on the visen pins are no longer attached to the load. when power is turned off to the load these (~100 ? ) fets turn on, thus some low current, (10ma) continues to be drawn from the supply in addition to the sleep load current resulting in a 4 o c die temperature rise. hip1011 high power circuit instances occur when a noncompliant card is designed for use in a pci environment. although the hip1011 family has proven to be very design flexible, controlling high power +12v supplies requires specia l attention. this is due to thermal considerations that limit the integrated power device on the +12v supply to about 1.5a. to address this an external add on circuit as shown in figure 8 enables the designer to add the oc monitoring and control of a high power +12v supply in addition to the 3 other power supplies. the hip1011 is represented by pin names in rectangles. this circuit primarily require s that an external p-channel mosfet be connected in parallel to the internal hip1011 pmos device and that the di screte device have a much lower r ds(on) value than the internal pmos device in order to carry the majority of the current load. by monitoring the voltage across the sense resistor carrying the combined load current of both the internal and external fets and by using a comparator with a common mode input voltage range to the positive rail and a low input voltage threshold offset to reduce distribution losses, a high precision oc detector can be designed to control a much higher current load than can be tolerated by the hip1011. an alternative circuit for moderate current levels where both accuracy and cost are lowered can be accomplished by a single external p-channel mosfet in parallel with the internal p-channel mosfet. for example, if 2x the oc level is desired a 0.3 ? r ds(on) p-channel mosfet can be used thus approximately do ubling the +12 iout before latch-off. ioc total = ioc internal (1 + r ds(on) of internal fet/r ds(on) of external fet). v supply figure 7. split load circuit vs visen pwron 3v5vg r1 r2 to sleep load to full load r sense q1 q2 system power mgt controller q3 + - fltn 12vo 12vin to +12v load 12vg figure 8. high power +12v circuit 12vin r2 r3 r1 r sense q1 q2
fn4640 rev 5.00 page 9 of 9 november 18, 2004 hip1011b intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2003-2004. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m ? m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - b 0.014 0.019 0.35 0.49 9 c 0.007 0.010 0.19 0.25 - d 0.386 0.394 9.80 10.00 3 e 0.150 0.157 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 ? 0 o 8 o 0 o 8 o - rev. 1 02/02
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